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| 9-BIT SHIFT REGISTER SY10E142 SY100E142 FEATURES s 700MHz min. shift frequency s Extended 100E VEE range of -4.2V to -5.5V s s s s 9 bits wide for byte-parity applications Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K input pulldown resistors s Fully compatible with Motorola MC10E/100E142 s Available in 28-pin PLCC package DESCRIPTION The SY10/100E142 are high-speed 9-bit shift registers designed for use in new, high-performance ECL systems. The E142 can accept serial or parallel data to be shifted out in one direction as both serial and parallel outputs. The nine inputs, D0-D8, accept parallel input data, while S-IN accepts serial input data. The SEL (Select) control pin serves to determine the mode of operation, either SHIFT or LOAD. The shift direction is from bit 0 to bit 8. The input data has to meet the set-up time before being clocked into the nine input registers on the rising edge of CLK1 or CLK2. Shifting is also performed on the rising edge of either CLK1 or CLK2. The MR (Master Reset) control signal asynchronously resets all nine registers to a logic LOW when a logic HIGH is applied to MR. The E142 is designed for applications such as diagnostic scan registers, parallel-to-serial conversions and is also suitable for byte-wide parity. BLOCK DIAGRAM S-IN D0 1 0 DQ Q0 PIN CONFIGURATION 1 D1 0 DQ Q1 1 D2 0 DQ Q2 25 24 23 22 21 20 19 MR 1 D3 0 DQ Q3 D8 D7 D6 D5 VCCO Q8 SEL 26 27 28 1 2 3 4 5 6 7 8 9 10 11 18 17 Q7 Q6 VCC Q5 VCCO Q4 Q3 1 D4 0 DQ Q4 CLK1 CLK2 VEE S-IN D0 D1 PLCC TOP VIEW J28-1 16 15 14 13 12 1 D5 0 DQ Q5 1 D6 0 DQ Q6 PIN NAMES DQ Q7 1 D7 0 Pin D0-D8 D4 VCCO 1 D8 SEL CLK1 CLK2 MR 0 DQ Q8 S-IN SEL CLK1, CLK2 MR Q0-Q8 VCCO Q0 Q1 Q2 D2 D3 Function Parallel Data Inputs Serial Data Input Mode Select Input Clock Inputs Master Reset Data Outputs VCC to Output Rev.: C Amendment: /1 1 Issue Date: February, 1998 Micrel SY10E142 SY100E142 TRUTH TABLE SEL L H MODE LOAD SHIFT DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol IIH IEE Parameter Input HIGH Current Power Supply Current 10E 100E -- -- 120 120 145 145 -- -- 120 120 145 145 -- -- 120 138 145 165 TA = +25C TA = +85C Max. 150 Unit A mA Condition -- -- Min. Typ. Max. Min. Typ. -- -- 150 -- -- Max. Min. Typ. 150 -- -- AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0C Symbol fSHIFT tPLH tPHL tS Parameter Max. Shift Frequency Propagation Delay to Output CLK MR Set-up Time D SEL Hold Time D SEL Reset Recovery Time Minimum Pulse Width CLK, MR Within-Device Skew Rise/Fall Time 20% to 80% TA = +25C TA = +85C Max. -- 1000 1000 ps 50 300 300 75 900 400 -- 300 -100 150 100 -150 700 -- 75 525 -- -- -- -- -- -- -- 800 50 300 300 75 900 400 -- 300 -100 150 100 -150 700 -- 75 525 -- -- -- -- -- -- -- 800 50 300 300 75 900 400 -- 300 -100 150 100 -150 700 -- 75 525 -- -- ps -- -- -- -- -- 800 ps ps ps ps -- -- 1 -- -- -- Unit MHz ps 600 600 800 800 1000 1000 600 600 800 800 1000 1000 600 600 800 800 Condition -- -- Min. Typ. Max. Min. Typ. 700 900 -- 700 900 Max. Min. Typ. -- 700 900 tH tRR tPW tskew tr tf NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code SY10E142JC SY10E142JCTR SY100E142JC SY100E142JCTR Package Type J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial 2 Micrel SY10E142 SY100E142 28 LEAD PLCC (J28-1) Rev. 03 3 Micrel SY10E142 SY100E142 MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA FAX + 1 (408) 980-9191 + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 2000 Micrel Incorporated 4 |
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